|Registers / Pin interrupt/pattern match engine register description|
The pattern match control register contains one bit to select pattern-match interrupt generation (as opposed to pin interrupts which share the same interrupt request lines), and another to enable the RXEV output to the cpu. This register also allows the current state of any pattern matches to be read.
If the pattern match feature is not used (either for interrupt generation or for RXEV assertion) bits SEL_PMATCH and ENA_RXEV of this register should be left at 0 to conserve power.
|0||SEL_PMATCH||Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.||0|
|0||Pin interrupt. Interrupts are driven in response to the standard pin interrupt function|
|1||Pattern match. Interrupts are driven in response to pattern matches.|
|1||ENA_RXEV||Enables the RXEV output to the ARM cpu and/or to a GPIO output when the specified boolean expression evaluates to true.||0|
|0||Disabled. RXEV output to the cpu is disabled.|
|1||Enabled. RXEV output to the cpu is enabled.|
|23:2||-||Reserved. Do not write 1s to unused bits.||0|
|31:24||PMAT||-||This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs.||0x0|
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