PINT IENR addressOffset = 0x004

For each of the 8 pin interrupts selected in the PINTSELn registers (see SYSCON PINTSEL addressOffset = 0x178), one bit in the IENR register enables the interrupt depending on the pin interrupt mode configured in the ISEL register:

  • If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is enabled.
  • If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is enabled. The IENF register configures the active level (HIGH or LOW) for this interrupt.
Table 1. PINT registerName = IENR addressOffset = 0x004
Bit Symbol Description Reset value Access
7:0 ENRL Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. 0 R/W
31:8 - Reserved. - -