PINT IENF addressOffset = 0x010

For each of the 8 pin interrupts selected in the PINTSELn registers (see SYSCON PINTSEL addressOffset = 0x178), one bit in the IENF register enables the falling edge interrupt or the configures the level sensitivity depending on the pin interrupt mode configured in the ISEL register:

  • If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is enabled.
  • If the pin interrupt mode is level sensitive (PMODE = 1), the active level of the level interrupt (HIGH or LOW) is configured.
Table 1. PINT registerName = IENF addressOffset = 0x010
Bit Symbol Description Reset value Access
7:0 ENAF Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. 0 R/W
31:8 - Reserved. - -