PINT CIENR addressOffset = 0x00C

For each of the 8 pin interrupts selected in the PINTSELn registers (see SYSCON PINTSEL addressOffset = 0x178), one bit in the CIENR register clears the corresponding bit in the IENR register depending on the pin interrupt mode configured in the ISEL register:

  • If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is cleared.
  • If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is cleared.
Table 1. PINT registerName = CIENR addressOffset = 0x00C
Bit Symbol Description Reset value Access
7:0 CENRL Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. NA WO
31:8 - Reserved. - -