|Registers / Pin interrupt/pattern match engine register description|
For each of the 8 pin interrupts selected in the PINTSELn registers (see SYSCON PINTSEL addressOffset = 0x178), one bit in the CIENR register clears the corresponding bit in the IENR register depending on the pin interrupt mode configured in the ISEL register:
|7:0||CENRL||Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.||NA||WO|
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