|Registers / Pin interrupt/pattern match engine register description|
For each of the 8 pin interrupts selected in the PINTSELn registers (see SYSCON PINTSEL addressOffset = 0x178), one bit in the CIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register:
|7:0||CENAF||Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.||NA||WO|
© NXP N.V. 2014. All rights reserved.