PINT CIENF addressOffset = 0x018

For each of the 8 pin interrupts selected in the PINTSELn registers (see SYSCON PINTSEL addressOffset = 0x178), one bit in the CIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register:

  • If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is cleared.
  • If the pin interrupt mode is level sensitive (PMODE = 1), the LOW-active interrupt is selected.
Table 1. PINT registerName = CIENF addressOffset = 0x018
Bit Symbol Description Reset value Access
7:0 CENAF Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. NA WO
31:8 - Reserved. - -