|Pin interrupt generator and pattern match engine (PINT) / PINT General description|
In this interrupt facility, up to 8 pins are identified as interrupt sources by the Pin Interrupt Select registers (PINTSEL0-7). All registers in the pin interrupt block contain 8 bits, corresponding to the pins called out by the PINTSEL0-7 registers. The ISEL register defines whether each interrupt pin is edge- or level-sensitive. The RISE and FALL registers detect edges on each interrupt pin, and can be written to clear (and set) edge detection. The IST register indicates whether each interrupt pin is currently requesting an interrupt, and this register can also be written to clear interrupts.
The other pin interrupt registers play different roles for edge-sensitive and level-sensitive pins, as described in PINT Pin interrupt registers for edge- and level-sensitive pins.
|Name||Edge-sensitive function||Level-sensitive function|
|IENR||Enables rising-edge interrupts.||Enables level interrupts.|
|SIENR||Write to enable rising-edge interrupts.||Write to enable level interrupts.|
|CIENR||Write to disable rising-edge interrupts.||Write to disable level interrupts.|
|IENF||Enables falling-edge interrupts.||Selects active level.|
|SIENF||Write to enable falling-edge interrupts.||Write to select high-active.|
|CIENF||Write to disable falling-edge interrupts.||Write to select low-active.|
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