NVIC ISPR0 addressOffset = 0x200

The ISPR0 register allows setting the pending state of the peripheral interrupts, or for reading the pending state of those interrupts. Clear the pending state of interrupts through the ICPR0 registers (NVIC ICPR0 addressOffset = 0x280).

The bit description is as follows for all bits in this register:

  • Write -

    Writing 0 has no effect, writing 1 changes the interrupt state to pending.

  • Read -

    0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.

Table 1. NVIC registerName = ISPR0 addressOffset = 0x200
Bit Symbol Description Reset value
0 ISP_SPI0 Interrupt pending set. 0
1 ISP_SPI1 Interrupt pending set. 0
2 - Reserved. -
3 ISP_UART0 Interrupt pending set. 0
4 ISP_UART1 Interrupt pending set. 0
5 ICE_UART2 Interrupt pending set. 0
6 - Reserved. -
7 - Reserved. -
8 ISP_I2C Interrupt pending set. 0
9 ISP_SCT Interrupt pending set. 0
10 ISP_MRT Interrupt pending set. 0
11 ISP_CMP Interrupt pending set. 0
12 ISP_WDT Interrupt pending set. 0
13 ISP_BOD Interrupt pending set. 0
14 ISP_FLASH Interrupt pending set. 0
15 ISP_WKT Interrupt pending set. 0
23:16 - Reserved. -
24 ISP_PININT0 Interrupt pending set. 0
25 ISP_PININT1 Interrupt pending set. 0
26 ISP_PININT2 Interrupt pending set. 0
27 ISP_PININT3 Interrupt pending set. 0
28 ISP_PININT4 Interrupt pending set. 0
29 ISP_PININT5 Interrupt pending set. 0
30 ISP_PININT6 Interrupt pending set. 0
31 ISP_PININT7 Interrupt pending set. 0

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