NVIC ISER0 addressOffset = 0x100

The ISER0 register allows to enable peripheral interrupts or to read the enabled state of those interrupts. Disable interrupts through the ICER0 (NVIC ICER0 addressOffset = 0x180).

The bit description is as follows for all bits in this register:

  • Write -

    Writing 0 has no effect, writing 1 enables the interrupt.

  • Read -

    0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

Table 1. NVIC registerName = ISER0 addressOffset = 0x100
Bit Symbol Description Reset value
0 ISE_SPI0 Interrupt enable. 0
1 ISE_SPI1 Interrupt enable. 0
2 - Reserved. -
3 ISE_UART0 Interrupt enable. 0
4 ISE_UART1 Interrupt enable. 0
5 ISE_UART2 Interrupt enable. 0
6 - Reserved. -
7 - Reserved. -
8 ISE_I2C Interrupt enable. 0
9 ISE_SCT Interrupt enable. 0
10 ISE_MRT Interrupt enable. 0
11 ISE_CMP Interrupt enable. 0
12 ISE_WDT Interrupt enable. 0
13 ISE_BOD Interrupt enable. 0
14 ISE_FLASH Interrupt enable. 0
15 ISE_WKT Interrupt enable. 0
23:16 - Reserved. -
24 ISE_PININT0 Interrupt enable. 0
25 ISE_PININT1 Interrupt enable. 0
26 ISE_PININT2 Interrupt enable. 0
27 ISE_PININT3 Interrupt enable. 0
28 ISE_PININT4 Interrupt enable. 0
29 ISE_PININT5 Interrupt enable. 0
30 ISE_PININT6 Interrupt enable. 0
31 ISE_PININT7 Interrupt enable. 0

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