NVIC IPR3 addressOffset = 0x40C

The IPR3 register controls the priority of four peripheral interrupts. Each interrupt can have one of 4 priorities, where 0 is the highest priority.

Table 1. NVIC registerName = IPR3 addressOffset = 0x40C
Bit Symbol Description
5:0 - These bits ignore writes, and read as 0.
7:6 IP_WDT Interrupt Priority. 0 = highest priority. 3 = lowest priority.
13:8 - These bits ignore writes, and read as 0.
15:14 IP_BOD Interrupt Priority. 0 = highest priority. 3 = lowest priority.
21:16 - These bits ignore writes, and read as 0.
23:22 IP_FLASH Interrupt Priority. 0 = highest priority. 3 = lowest priority.
29:24 - These bits ignore writes, and read as 0.
31:30 IP_WKT Interrupt Priority. 0 = highest priority. 3 = lowest priority.

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