NVIC ICPR0 addressOffset = 0x280

The ICPR0 register allows clearing the pending state of the peripheral interrupts, or for reading the pending state of those interrupts. Set the pending state of interrupts through the ISPR0 register (NVIC ISPR0 addressOffset = 0x200).

The bit description is as follows for all bits in this register:

  • Write -

    Writing 0 has no effect, writing 1 changes the interrupt state to not pending.

  • Read -

    0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.

Table 1. NVIC registerName = ICPR0 addressOffset = 0x280
Bit Symbol Function Reset value
0 ICP_SPI0 Interrupt pending clear. 0
1 ICP_SPI1 Interrupt pending clear. 0
2 - Reserved. -
3 ICP_UART0 Interrupt pending clear. 0
4 ICP_UART1 Interrupt pending clear. 0
5 ICP_UART2 Interrupt pending clear. 0
6 - Reserved. -
7 - Reserved. -
8 ICP_I2C Interrupt pending clear. 0
9 ICP_SCT Interrupt pending clear. 0
10 ICP_MRT Interrupt pending clear. 0
11 ICP_CMP Interrupt pending clear. 0
12 ICP_WDT Interrupt pending clear. 0
13 ICP_BOD Interrupt pending clear. 0
14 ICP_FLASH Interrupt pending clear. 0
15 ICP_WKT Interrupt pending clear. 0
23:16 - Reserved. -
24 ICP_PININT0 Interrupt pending clear. 0
25 ICP_PININT1 Interrupt pending clear. 0
26 ICP_PININT2 Interrupt pending clear. 0
27 ICP_PININT3 Interrupt pending clear. 0
28 ICP_PININT4 Interrupt pending clear. 0
29 ICP_PININT5 Interrupt pending clear. 0
30 ICP_PININT6 Interrupt pending clear. 0
31 ICP_PININT7 Interrupt pending clear. 0

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