NVIC ICER0 addressOffset = 0x180

The ICER0 register allows disabling the peripheral interrupts, or for reading the enabled state of those interrupts. Enable interrupts through the ISER0 registers (NVIC ISER0 addressOffset = 0x100).

The bit description is as follows for all bits in this register:

  • Write -

    Writing 0 has no effect, writing 1 disables the interrupt.

  • Read -

    0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

Table 1. NVIC Interrupt clear enable register 0 (ICER0, address 0xE000 E180)
Bit Symbol Description Reset value
0 ICE_SPI0 Interrupt disable. 0
1 ICE_SPI1 Interrupt disable. 0
2 - Reserved. -
3 ICE_UART0 Interrupt disable. 0
4 ICE_UART1 Interrupt disable. 0
5 ICE_UART2 Interrupt disable. 0
6 - Reserved. -
7 - Reserved. -
8 ICE_I2C Interrupt disable. 0
9 ICE_SCT Interrupt disable. 0
10 ICE_MRT Interrupt disable. 0
11 ICE_CMP Interrupt disable. 0
12 ICE_WDT Interrupt disable. 0
13 ICE_BOD Interrupt disable. 0
14 ICE_FLASH Interrupt disable. 0
15 ICE_WKT Interrupt disable. 0
23:16 - Reserved. -
24 ICE_PININT0 Interrupt disable. 0
25 ICE_PININT1 Interrupt disable. 0
26 ICE_PININT2 Interrupt disable. 0
27 ICE_PININT3 Interrupt disable. 0
28 ICE_PININT4 Interrupt disable. 0
29 ICE_PININT5 Interrupt disable. 0
30 ICE_PININT6 Interrupt disable. 0
31 ICE_PININT7 Interrupt disable. 0

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