NVIC IABR0 addressOffset = 0x300

The IABR0 register is a read-only register that allows reading the active state of the peripheral interrupts. Use this register to determine which peripherals are asserting an interrupt to the NVIC and may also be pending if there are enabled.

The bit description is as follows for all bits in this register:

  • Write -

    n/a.

  • Read -

    0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.

Table 1. NVIC registerName = IABR0 addressOffset = 0x300
Bit Symbol Function Reset value
0 IAB_SPI0 Interrupt active. 0
1 IAB_SPI1 Interrupt active. 0
2 - Reserved. -
3 IAB_UART0 Interrupt active. 0
4 IAB_UART1 Interrupt active. 0
5 IAB_UART2 Interrupt active. 0
6 - Reserved. -
7 - Reserved. -
8 IAB_I2C Interrupt active. 0
9 IAB_SCT Interrupt active. 0
10 IAB_MRT Interrupt active. 0
11 IAB_CMP Interrupt active. 0
12 IAB_WDT Interrupt active. 0
13 IAB_BOD Interrupt active. 0
14 IAB_FLASH Interrupt active. 0
15 IAB_WKT Interrupt active. 0
23:16 - Reserved. -
24 IAB_PININT0 Interrupt active. 0
25 IAB_PININT1 Interrupt active. 0
26 IAB_PININT2 Interrupt active. 0
27 IAB_PININT3 Interrupt active. 0
28 IAB_PININT4 Interrupt active. 0
29 IAB_PININT5 Interrupt active. 0
30 IAB_PININT6 Interrupt active. 0
31 IAB_PININT7 Interrupt active. 0

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