NVIC General description

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0+. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.

Interrupt sources

NVIC Connection of interrupt sources to the NVIC lists the interrupt sources for each peripheral function. Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may represent more than one interrupt source. Interrupts with the same priority level are serviced in the order of their interrupt number.

See Nested Vectored Interrupt Controller (NVIC) for a detailed description of the NVIC and the NVIC register description.

Table 1. NVIC Connection of interrupt sources to the NVIC
Interrupt number Name Description Flags
0 SPI0_IRQ SPI0 interrupt

See SPI registerName = INTENSET addressOffset = 0x00C.

1 SPI1_IRQ SPI1 interrupt Same as SPI0_IRQ
2 - Reserved -
3 UART0_IRQ USART0 interrupt See USART registerName = INTENSET addressOffset = 0x00C
4 UART1_IRQ USART1 interrupt Same as UART0_IRQ
5 UART2_IRQ USART2 interrupt Same as UART0_IRQ
6 - Reserved -
7 - Reserved -
8 I2C0_IRQ I2C0 interrupt

See I2C Interrupt Enable Clear register (INTENCLR, address 0x4005 000C) bit description .

9 SCT_IRQ State configurable timer interrupt EVFLAG SCT event
10 MRT_IRQ Multi-rate timer interrupt Global MRT interrupt.

GFLAG0

GFLAG1

GFLAG2

GFLAG3

11 CMP_IRQ Analog comparator interrupt COMPEDGE - rising, falling, or both edges can set the bit
12 WDT_IRQ Windowed watchdog timer interrupt WARNINT - watchdog warning interrupt
13 BOD_IRQ BOD interrupts BODINTVAL - BOD interrupt level
14 - - Reserved
15 WKT_IRQ Self wake-up timer interrupt ALARMFLAG
23:16 - Reserved -
24 PININT0_IRQ Pin interrupt 0 or pattern match engine slice 0 interrupt PSTAT - pin interrupt status
25 PININT1_IRQ Pin interrupt 1 or pattern match engine slice 1 interrupt PSTAT - pin interrupt status
26 PININT2_IRQ Pin interrupt 2 or pattern match engine slice 2 interrupt PSTAT - pin interrupt status
27 PININT3_IRQ Pin interrupt 3 or pattern match engine slice 3 interrupt PSTAT - pin interrupt status
28 PININT4_IRQ Pin interrupt 4 or pattern match engine slice 4 interrupt PSTAT - pin interrupt status
29 PININT5_IRQ Pin interrupt 5 or pattern match engine slice 5 interrupt PSTAT - pin interrupt status
30 PININT6_IRQ Pin interrupt 6 or pattern match engine slice 6 interrupt PSTAT - pin interrupt status
31 PININT7_IRQ Pin interrupt 7 or pattern match engine slice 7 interrupt PSTAT - pin interrupt status

Non-Maskable Interrupt (NMI)

The LPC81x supports the NMI, which can be triggered by an peripheral interrupt or triggered by software. The NMI has the highest priority exception other than the reset.

You can set up any peripheral interrupt listed in NVIC Connection of interrupt sources to the NVIC as NMI using the NMISRC register in the SYSCON block (SYSCON registerName = NMISRC addressOffset = 0x174). To avoid using the same peripheral interrupt as NMI exception and normal interrupt, disable the interrupt in the NVIC when you configure it as NMI.

Vector table offset

The vector table contains the reset value of the stack pointer and the start addresses, also called exception vectors, for all exception handlers. On system reset, the vector table is located at address 0x0000 0000. Software can write to the VTOR register in the NVIC to relocate the vector table start address to a different memory location.


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