NVIC Features

  • Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0+.
  • Tightly coupled interrupt controller provides low interrupt latency.
  • Controls system exceptions and peripheral interrupts.
  • The NVIC supports 32 vectored interrupts.
  • Four programmable interrupt priority levels with hardware priority level masking.
  • Software interrupt generation using the ARM exceptions SVCall and PendSV.
  • Support for NMI.
  • ARM Cortex M0+ Vector table offset register VTOR implemented.

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