|Registers / MRT Register description|
This register indicates the status of each MRT.
|0||INTFLAG||Monitors the interrupt flag.||0|
|0||No pending interrupt. Writing a zero is equivalent to no operation.|
|1||Pending interrupt. The interrupt is pending because TIMERn
has reached the end of the time interval. If the INTEN bit in the
CONTROLn is also set to 1, the interrupt for timer channel n and
the global interrupt are raised.
Writing a 1 to this bit clears the interrupt request.
|1||RUN||Indicates the state of TIMERn. This bit is read-only.||0|
|0||Idle state. TIMERn is stopped.|
|1||Running. TIMERn is running.|
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