MRT Register and register bit mapping

Register Offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
INTVAL0 0x0 IVALUE LOAD
TIMER0 0x4 VALUE  
CTRL0 0x8 INTEN MODE  
STAT0 0xC INTFLAG RUN  
INTVAL1 0x10 IVALUE LOAD
TIMER1 0x14 VALUE  
CTRL1 0x18 INTEN MODE  
STAT1 0x1C INTFLAG RUN  
INTVAL2 0x20 IVALUE LOAD
TIMER2 0x24 VALUE  
CTRL2 0x28 INTEN MODE  
STAT2 0x2C INTFLAG RUN  
INTVAL3 0x30 IVALUE LOAD
TIMER3 0x34 VALUE  
CTRL3 0x38 INTEN MODE  
STAT3 0x3C INTFLAG RUN  
IDLE_CH 0xF4   CHAN  
IRQ_FLAG 0xF8 GFLAG0 GFLAG1 GFLAG2 GFLAG3  

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