MRT IRQ_FLAG addressOffset = 0x0F8

The global interrupt register combines the interrupt flags from the individual timer channels in one register. Setting and clearing each flag behaves in the same way as setting and clearing the INTFLAG bit in each of the STATUSn registers.

Table 1. MRT registerName = IRQ_FLAG addressOffset = 0x0F8
Bit Symbol Value Description Reset value
0 GFLAG0   Monitors the interrupt flag of TIMER0. 0
    0 No pending interrupt. Writing a zero is equivalent to no operation.  
    1 Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised.

Writing a 1 to this bit clears the interrupt request.

 
1 GFLAG1   Monitors the interrupt flag of TIMER1. 0
    0 No pending interrupt. Writing a zero is equivalent to no operation.  
    1 Pending interrupt. The interrupt is pending because TIMER1 has reached the end of the time interval. If the INTEN bit in the CONTROL1 register is also set to 1, the interrupt for timer channel 1 and the global interrupt are raised.

Writing a 1 to this bit clears the interrupt request.

 
2 GFLAG2   Monitors the interrupt flag of TIMER2. 0
    0 No pending interrupt. Writing a zero is equivalent to no operation.  
    1 Pending interrupt. The interrupt is pending because TIMER2 has reached the end of the time interval. If the INTEN bit in the CONTROL2 register is also set to 1, the interrupt for timer channel 2 and the global interrupt are raised.

Writing a 1 to this bit clears the interrupt request.

 
3 GFLAG3   Monitors the interrupt flag of TIMER3. 0
    0 No pending interrupt. Writing a zero is equivalent to no operation.  
    1 Pending interrupt. The interrupt is pending because TIMER3 has reached the end of the time interval. If the INTEN bit in the CONTROL3 register is also set to 1, the interrupt for timer channel 3 and the global interrupt are raised.

Writing a 1 to this bit clears the interrupt request.

 
31:4 -   Reserved. 0

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