The LPC81x incorporates several distinct memory regions. Memory map shows the overall map of the entire address space from the user program viewpoint following reset.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral is allocated 16 kB of space simplifying the address decoding.
The registers incorporated into the ARM Cortex-M0+ core, such as NVIC, SysTick, and sleep mode control, are located on the private peripheral bus.
The GPIO port and pin interrupt/pattern match registers are accessed by the ARM Cortex-M0+ single-cycle I/O enabled port (IOP).
The private peripheral bus includes the ARM Cortex-M0+ peripherals such as the NVIC, SysTick, and the core control registers.
LPC81x Memory mapping
The LPC81x supports the ARM Cortex-M0+ Micro Trace Buffer. See DEBUG Micro Trace Buffer (MTB).
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