|ROM API functions / ISP-IAP API|
Most IAP and ISP commands operate on sectors and specify sector numbers. In addition a page erase command is supported. The following table shows the correspondence between page numbers, sector numbers, and memory addresses.
The size of a sector is 1 kB and the size of a page is 64 Byte. One sector contains 16 pages.
|Sector number||Sector size [kB]||Page number||Address range||4 kB flash||8 kB flash||16 kB flash|
|0||1||0 -15||0x0000 0000 - 0x0000 03FF||yes||yes||yes|
|1||1||16 - 31||0x0000 0400 - 0x0000 07FF||yes||yes||yes|
|2||1||32 - 47||0x0000 0800 - 0x0000 0BFF||yes||yes||yes|
|3||1||48 - 63||0x0000 0C00 - 0x0000 0FFF||yes||yes||yes|
|4||1||64 - 79||0x0000 1000 - 0x0000 13FF||-||yes||yes|
|5||1||80 - 95||0x0000 1400 - 0x0000 17FF||-||yes||yes|
|6||1||96 - 111||0x0000 1800 - 0x0000 1BFF||-||yes||yes|
|7||1||112 - 127||0x0000 1C00 - 0x0000 1FFF||-||yes||yes|
|8||1||128 - 143||0x0000 2000 - 0x0000 23FF||-||-||yes|
|9||1||144 - 159||0x0000 2400 - 0x0000 27FF||-||yes|
|10||1||160 - 175||0x0000 2800 - 0x0000 2BFF||-||yes|
|11||1||176 - 191||0x0000 2C00 - 0x0000 2FFF||-||yes|
|12||1||192 - 207||0x0000 3000 - 0x0000 33FF||-||yes|
|13||1||208 - 223||0x0000 3400 - 0x0000 37FF||-||yes|
|14||1||224 - 239||0x0000 3800 - 0x0000 3BFF||-||yes|
|15||1||240 - 255||0x0000 3C00 - 0x0000 3FFF||-||yes|
The part is equipped with the Error Correction Code (ECC) capable Flash memory. The purpose of an error correction module is twofold:
The ECC first decodes data words read from the memory into output data words. Then, the ECC encodes data words to be written to the memory. The error correction capability consists of single bit error correction with Hamming code.
The operation of the ECC is transparent to the running application. The ECC content itself is stored in a flash memory not accessible by the user’s code to either read from it or write into it on its own. 6 bit of ECC corresponds to every consecutive 32 bit of the user accessible Flash. Consequently, Flash bytes from 0x0000 0000 to 0x0000 0003 are protected by the first 6 bit ECC, Flash bytes from 0x0000 0004 to 0x0000 0007 are protected by the second 6-bit ECC byte, etc.
Whenever the CPU requests a read from the user accessible Flash, both 32 bits of raw data containing the specified memory location and the matching ECC byte are evaluated. If the ECC mechanism detects a single error in the fetched data, a correction will be applied before data are provided to the CPU. When a write request into the user accessible Flash is made, writing the user specified content is accompanied by a matching ECC value calculated and stored in the ECC memory.
When a sector of Flash memory is erased, the corresponding ECC bits are also erased. Once a 6-bit ECC is written, it can not be updated unless it is erased first. Therefore, for the implemented ECC mechanism to perform properly, data must be written into the flash memory in groups of 4 bytes (or multiples of 4), aligned as described above.
Code Read Protection is a mechanism that allows the user to enable different levels of security in the system so that access to the on-chip flash and use of the ISP can be restricted. When needed, CRP is invoked by programming a specific pattern in flash location at 0x0000 02FC. IAP commands are not affected by the code read protection.
Important: any CRP change becomes effective only after the device has gone through a power cycle.
|Name||Pattern programmed in 0x0000 02FC||Description|
|NO_ISP||0x4E69 7370||Prevents sampling of the ISP entry pin for entering ISP mode. The ISP entry pin is available for other uses.|
|CRP1||0x12345678||Access to chip via the SWD pins is disabled. This mode allows
partial flash update using the following ISP commands and restrictions:
This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. Since compare command is disabled in case of partial updates the secondary loader should implement checksum mechanism to verify the integrity of the flash.
|CRP2||0x87654321||Access to chip via the SWD pins is disabled. The following
ISP commands are disabled:
When CRP2 is enabled the ISP erase command only allows erasure of all user sectors.
|CRP3||0x43218765||Access to chip via the SWD pins is disabled. ISP entry by
pulling the ISP entry pin LOW is disabled if a valid user code is
present in flash sector 0.
This mode effectively disables ISP override using the ISP entry pin. It is up to the user’s application to provide a flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART.
Caution: If CRP3 is selected, no future factory testing can be performed on the device.
|CRP option||User Code Valid||ISP entry pin at reset||SWD enabled||Part enters ISP mode||partial flash update in ISP mode|
|ISP command||CRP1||CRP2||CRP3 (no entry in ISP mode allowed)|
|Set Baud Rate||yes||yes||n/a|
|Write to RAM||yes; above 0x1000 0300 only||no||n/a|
|Prepare sector(s) for write operation||yes||yes||n/a|
|Copy RAM to flash||yes; not to sector 0||no||n/a|
|Erase sector(s)||yes; sector 0 can only be erased when all sectors are erased.||yes; all sectors only||n/a|
|Blank check sector(s)||no||no||n/a|
|Read Part ID||yes||yes||n/a|
|Read Boot code version||yes||yes||n/a|
In case a CRP mode is enabled and access to the chip is allowed via the ISP, an unsupported or restricted ISP command will be terminated with return code CODE_READ_PROTECTION_ENABLED.
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