INTRO Pin description

The pin description table shows the pin functions that are fixed to specific pins on each package. These fixed-pin functions are selectable between the GPIO and the RESET, comparator, SWD, and XTAL pins. By default, the GPIO function is selected except on pins PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in boundary scan mode only.

Movable function for the I2C, USART, SPI, and SCT pin functions can be assigned through the switch matrix to any pin that is not power or ground in place of the pin’s fixed functions.

The following exceptions apply:

For full I2C-bus compatibility, assign the I2C functions to the open-drain pins PIO0_11 and PIO0_10.

Do not assign more than one output to any pin. However, more than one input can be assigned to a pin. Once any function is assigned to a pin, the pin’s GPIO functionality is disabled.

Pin PIO0_4 triggers a wake-up from Deep power-down mode. If you need to wake up from Deep power-down mode via an external pin, do not assign any movable function to this pin.

The JTAG functions TDO, TDI, TCK, TMS, and TRST are selected on pins PIO0_0 to PIO0_4 by hardware when the part is in boundary scan mode.

Table 1. INTRO Pin description table (fixed pins)
Symbol SO20/ TSSOP20 TSSOP16 Type Reset state Description  
PIO0_0/ACMP_I1/ TDO 19 16 I/O I; PU PIO0_0

General purpose digital input/output port 0 pin 0.

In ISP mode, this is the USART0 receive pin U0_RXD. In boundary scan mode: TDO (Test Data Out).

5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.
      AI - ACMP_I1

Analog comparator input 1.

 
PIO0_1/ACMP_I2/ CLKIN/TDI 12 9 I/O I; PU PIO0_1

General purpose digital input/output pin. In boundary scan mode: TDI (Test Data In). ISP entry pin on chip versions 1A and 2A Boot ROM Pin description.

5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.
      AI - ACMP_I2

Analog comparator input 2.

 
      I - CLKIN

External clock input.

 
SWDIO/PIO0_2/TMS 7 6 I/O I; PU SWDIO

Serial Wire Debug I/O. SWDIO is enabled by default on this pin. In boundary scan mode: TMS (Test Mode Select).

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes high-current output driver.
      I/O - PIO0_2

General purpose digital input/output pin.

 
SWCLK/PIO0_3/ TCK 6 5 I/O I; PU SWCLK

Serial Wire Clock. SWCLK is enabled by default on this pin. In boundary scan mode: TCK (Test Clock).

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes high-current output driver.
      I/O - PIO0_3

General purpose digital input/output pin.

 
PIO0_4/WAKEUP/ TRST 5 4 I/O I; PU PIO0_4

General purpose digital input/output pin.

In ISP mode, this is the USART0 transmit pin U0_TXD.

In boundary scan mode: TRST (Test Reset).

This pin triggers a wake-up from Deep power-down mode. If you need to wake up from Deep power-down mode via an external pin, do not assign any movable function to this pin. Pull this pin HIGH externally to enter Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. In Deep power-down mode, pulling this pin LOW wakes up the chip.
RESET/PIO0_5 4 3 I/O I; PU RESET

External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.
      I - PIO0_5

General purpose digital input/output pin.

 
PIO0_6/VDDCMP 18 15 I/O I; PU PIO0_6

General purpose digital input/output pin.

The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is disabled .
      AI - VDDCMP

Alternate reference voltage for the analog comparator.

 
PIO0_7 17 14 I/O I; PU PIO0_7

General purpose digital input/output pin.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes high-current output driver.
PIO0_8/XTALIN 14 11 I/O I; PU PIO0_8

General purpose digital input/output pin.

5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O for the system oscillator. When configured as an analog I/O, the digital section of the pin is disabled, and the pin is not 5 V tolerant.
      I - XTALIN

Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.95 V.

 
PIO0_9/XTALOUT 13 10 I/O I; PU PIO0_9

General purpose digital input/output pin.

5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O for the system oscillator. When configured as an analog I/O, the digital section of the pin is disabled, and the pin is not 5 V tolerant.
      O - XTALOUT

Output from the oscillator circuit.

 
PIO0_10 9 8 I IA PIO0_10

General purpose digital input/output pin. Assign I2C functions to this pin when true open-drain pins are needed for a signal compliant with the full I2C specification.

True open-drain pin. I^ 2C-bus pins compliant with the I^ 2C-bus specification for I^ 2C standard mode, I^ 2C Fast-mode, and I^ 2C Fast-mode Plus. Do not use this pad for high-speed applications such as SPI or USART.

Note: If this pin is not available on the package, prevent it from internally floating as follows: Set bits 10 and 11 in the GPIO DIR0 register to 1 to enable the output driver and write 1 to bits 10 and 11 in the GPIO CLR0 register to drive the outputs LOW internally.
PIO0_11 8 7 I IA PIO0_11

General purpose digital input/output pin. Assign I2C functions to this pin when true open-drain pins are needed for a signal compliant with the full I2C specification.

True open-drain pin. I^ 2C-bus pins compliant with the I^ 2C-bus specification for I^ 2C standard mode, I^ 2C Fast-mode, and I^ 2C Fast-mode Plus. Do not use this pad for high-speed applications such as SPI or USART.

Note: If this pin is not available on the package, prevent it from internally floating as follows: Set bits 10 and 11 in the GPIO DIR0 register to 1 to enable the output driver and write 1 to bits 10 and 11 in the GPIO CLR0 register to drive the outputs LOW internally.
PIO0_12 3 2 I/O I; PU PIO0_12

General purpose digital input/output pin. ISP entry pin on the SO20/TSSOP20/TSSOP16 packages starting with chip version 4C (see <p id="CACHJEHC" class="- topic/p ">Boot process flowchart</p> </p>). A LOW level on this pin during reset starts the ISP command handler.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes high-current output driver.
PIO0_13 2 1 I/O I; PU PIO0_13

General purpose digital input/output pin.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes high-current output driver.
PIO0_14 20 - I/O I; PU PIO0_14

General purpose digital input/output pin.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
PIO0_15 11 - I/O I; PU PIO0_15

General purpose digital input/output pin.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
PIO0_16 10 - I/O I; PU PIO0_16

General purpose digital input/output pin.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
PIO0_17 1 - I/O I; PU PIO0_17

General purpose digital input/output pin.

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
V_ DD 15 12 - - 3.3 V supply voltage.  
V_ SS 16 13   - Ground.  

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