ARM Cortex M0+ instruction set

The processor implements the ARMv6-M Thumb instruction set, including a number of 32-bit instructions that use Thumb-2 technology. The ARMv6-M instruction set contains:

  • all of the 16-bit Thumb instructions from ARMv7-M excluding CBZ, CBNZ and IT.
  • the 32-bit Thumb instructions BL, DMB, DSB, ISB, MRS and MSR.

The Cortex M0+ instruction set shows the Cortex-M0+ instructions and their cycle counts. The cycle counts are based on a system with zero wait-states.

Table 1. Cortex M0+ instruction summary
Operation Description Assembler Cycles Notes
Move 8-bit immediate MOVS Rd, #<imm> 1  
Lo to Lo MOVS Rd, Rm 1  
Any to Any MOV Rd, Rm 1  
Any to PC MOV PC, Rm 2  
Add 3-bit immediate ADDS Rd, Rn, #<imm> 1  
All registers Lo ADDS Rd, Rn, Rm 1  
Any to Any ADD Rd, Rd, Rm 1  
Any to PC ADD PC, PC, Rm 2  
8-bit immediate ADDS Rd, Rd, #<imm> 1  
With carry ADCS Rd, Rd, Rm 1  
Immediate to SP ADD SP, SP, #<imm> 1  
Form address from SP ADD Rd, SP, #<imm> 1  
Form address from PC ADR Rd, <label> 1  
Subtract Lo and Lo SUBS Rd, Rn, Rm 1  
3-bit immediate SUBS Rd, Rn, #<imm> 1  
8-bit immediate SUBS Rd, Rd, #<imm> 1  
With carry SBCS Rd, Rd, Rm 1  
Immediate from SP SUB SP, SP, #<imm> 1  
Negate RSBS Rd, Rn, #0 1  
Multiply Multiply MULS Rd, Rm, Rd 1  
Compare Compare CMP Rn, Rm 1  
Negative CMN Rn, Rm 1  
Immediate CMP Rn, #<imm> 1  
Logical AND ANDS Rd, Rd, Rm 1  
Exclusive OR EORS Rd, Rd, Rm 1  
OR ORRS Rd, Rd, Rm 1  
Bit clear BICS Rd, Rd, Rm 1  
Move NOT MVNS Rd, Rm 1  
AND test TST Rn, Rm 1  
Shift Logical shift left by immediate LSLS Rd, Rm, #<shift> 1  
Logical shift left by register LSLS Rd, Rd, Rs 1  
Logical shift right by immediate LSRS Rd, Rm, #<shift> 1  
Logical shift right by register LSRS Rd, Rd, Rs 1  
Arithmetic shift right ASRS Rd, Rm, #<shift> 1  
Arithmetic shift right by register ASRS Rd, Rd, Rs 1  
Rotate Rotate right by register RORS Rd, Rd, Rs 1  
Load Word, immediate offset LDR Rd, [Rn, #<imm>] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
Halfword, immediate offset LDRH Rd, [Rn, #<imm>] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
Byte, immediate offset LDRB Rd, [Rn, #<imm>] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
Word, register offset LDR Rd, [Rn, Rm] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
Halfword, register offset LDRH Rd, [Rn, Rm] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
Signed halfword, register offset LDRSH Rd, [Rn, Rm] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
Byte, register offset LDRB Rd, [Rn, Rm] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
Signed byte, register offset LDRSB Rd, [Rn, Rm] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
PC-relative LDR Rd, <label> 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
SP-relative LDR Rd, [SP, #<imm>] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
Multiple, excluding base LDM Rn!, {<loreglist>} 1 + N N is the number of elements in the list.
Multiple, including base LDM Rn, {<loreglist>} 1 + N N is the number of elements in the list.
Store Word, immediate offset STR Rd, [Rn, #<imm>] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
Halfword, immediate offset STRH Rd, [Rn, #<imm>] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
Byte, immediate offset STRB Rd, [Rn, #<imm>] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
Word, register offset STR Rd, [Rn, Rm] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
Halfword, register offset STRH Rd, [Rn, Rm] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
Byte, register offset STRB Rd, [Rn, Rm] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
SP-relative STR Rd, [SP, #<imm>] 2 or 1 2 cycles if to AHB interface or SCS, 1 cycle if to single-cycle I/O port.
Multiple STM Rn!, {<loreglist>} 1 + N N is the number of elements in the list.
Push Push PUSH {<loreglist>} 1 + N N is the number of elements in the list.
Push with link register PUSH {<loreglist>, LR} 1 + N N is the number of elements in the list including PC or LR..
Pop Pop POP {<loreglist>} 1 + N N is the number of elements in the list.
Pop and return POP {<loreglist>, PC} 3 + N N is the number of elements in the list including PC or LR..
Branch Conditional B<cc> <label> 1 or 2 2 if taken, 1 if not taken.
Unconditional B <label> 2  
With link BL <label> 3  
With exchange BX Rm 2  
With link and exchange BLX Rm 2  
Extend Signed halfword to word SXTH Rd, Rm 1  
Signed byte to word SXTB Rd, Rm 1  
Unsigned halfword UXTH Rd, Rm 1  
Unsigned byte UXTB Rd, Rm 1  
Reverse Bytes in word REV Rd, Rm 1  
Bytes in both halfwords REV16 Rd, Rm 1  
Signed bottom half word REVSH Rd, Rm 1  
State change Supervisor Call SVC #<imm> - Cycle count depends on core and debug configuration.
Disable interrupts CPSID i 1  
Enable interrupts CPSIE i 1  
Read special register MRS Rd, <specreg> 3  
Write special register MSR <specreg>, Rn 3  
Breakpoint BKPT #<imm> - Cycle count depends on core and debug configuration.
Hint Send event SEV 1  
Wait for interrupt WFI 2 Excludes time spend waiting for an interrupt or event.
Wait for event WFE 2 Excludes time spend waiting for an interrupt or event.
Yield YIELD 1 Executes as NOP.
No operation NOP 1  
Barriers Instruction synchronization ISB 3  
Data memory DMB 3  
Data synchronization DSB 3  

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