I2C STAT addressOffset = 0x004

The STAT register provides status flags and state information about all of the functions of the I^ 2C block. Some information in this register is read-only and some flags can be cleared by writing a 1 to them.

Access to bits in this register varies. RO = Read-only, W1 = write 1 to clear.

Details on the master and slave states described in the MSTSTATE and SLVSTATE bits in this register are listed in I2C Master function state codes (MSTSTATE) and I2C Slave function state codes (SLVSTATE).

Table 1. I2C registerName = STAT addressOffset = 0x004
Bit Symbol Value Description Reset value Access
0 MSTPENDING   Master Pending. Indicates that the Master is waiting to continue communication on the I2C bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. If the master is in the idle state, and no communication is needed, mask this interrupt. 1 RO
    0 In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.    
    1 Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.    
3:1 MSTSTATE   Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. 0 RO
    0x0 Idle. The Master function is available to be used for a new transaction.    
    0x1 Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.    
    0x2 Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.    
    0x3 NACK Address. Slave NACKed address.    
    0x4 NACK Data. Slave NACKed transmitted data.    
4 MSTARBLOSS   Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 0 W1
    0 No loss. No Arbitration Loss has occurred.    
    1 Arbitration loss. The Master function has experienced an Arbitration Loss.

At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.

   
5 -   Reserved. Read value is undefined, only zero should be written. NA NA
6 MSTSTSTPERR   Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MstContinue. 0 W1
    0 No Start/Stop Error has occurred.    
    1 Start/stop error has occurred. The Master function has experienced a Start/Stop Error.

A Start or Stop was detected at a time when it is not allowed by the I^ 2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.

   
7 -   Reserved. Read value is undefined, only zero should be written. NA NA
8 SLVPENDING   Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. 0 RO
    0 In progress. The Slave function does not currently need service.    
    1 Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.    
10:9 SLVSTATE   Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. 0 RO
    0x0 Slave address.. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.    
    0x1 Slave receive. Received data is available (Slave Receiver mode).    
    0x2 Slave transmit. Data can be transmitted (Slave Transmitter mode).    
    0x3 Reserved.    
11 SLVNOTSTR   Slave Not Stretching. Indicates when the slave function is stretching the I^ 2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. 1 RO
    0 Stretching. The slave function is currently stretching the I^ 2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.    
    1 Not stretching. The slave function is not currently stretching the I^ 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.    
13:12 SLVIDX   Slave address match Index. This field is valid when the I ^ 2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. 0 RO
    0x0 Slave address 0 was matched.    
    0x1 Slave address 1 was matched.    
    0x2 Slave address 2 was matched.    
    0x3 Slave address 3 was matched.    
14 SLVSEL   Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, or when there is a Stop detected on the bus. SLVSEL is not cleared if software NACKs data. 0 RO
    0 Not selected. The Slave function is not currently selected.    
    1 Selected. The Slave function is currently selected.    
15 SLVDESEL   Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. 0 W1
    0 Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.    
    1 Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.    
16 MONRDY   Monitor Ready. This flag is cleared when the MONRXDAT register is read. 0 RO
    0 No data. The Monitor function does not currently have data available.    
    1 Data waiting. The Monitor function has data waiting to be read.    
17 MONOV   Monitor Overflow flag. 0 W1
    0 No overrun. Monitor data has not overrun.    
    1 Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.    
18 MONACTIVE   Monitor Active flag. This flag indicates when the Monitor function considers the I^ 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. 0 RO
    0 Inactive. The Monitor function considers the I^ 2C bus to be inactive.    
    1 Active. The Monitor function considers the I^ 2C bus to be active.    
19 MONIDLE   Monitor Idle flag. This flag is set when the Monitor function sees the I^ 2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register . The flag can be cleared by writing a 1 to this bit. 0 W1
    0 Not idle. The I^ 2C bus is not idle, or this flag has been cleared by software.    
    1 Idle. The I^ 2C bus has gone idle at least once since the last time this flag was cleared by software.    
23:20 -   Reserved. Read value is undefined, only zero should be written. NA NA
24 EVENTTIMEOUT   Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C bus is idle. 0 W1
    0 No time-out. I^ 2C bus events have not caused a time-out.    
    1 Event time-out. The time between I^ 2C bus events has been longer than the time specified by the I2C TIMEOUT register.    
25 SCLTIMEOUT   SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. 0 W1
    0 No time-out. SCL low time has not caused a time-out.    
    1 Time-out. SCL low time has caused a time-out.    
31:26 -   Reserved. Read value is undefined, only zero should be written. NA NA

Table 2. I2C Master function state codes (MSTSTATE)
MstState Description Actions
0 Idle. The Master function is available to be used for a new transaction. Send a Start or disable MSTPENDING interrupt if the Master function is not needed currently.
1 Received data is available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. Read data and either continue, send a Stop, or send a Repeated Start.
2 Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. Send data and continue, or send a Stop or Repeated Start.
3 Slave NACKed address. Send a Stop or Repeated Start.
4 Slave NACKed transmitted data. Send a Stop or Repeated Start.
Table 3. I2C Slave function state codes (SLVSTATE)
SlvState Description Actions
0 Address plus R/W received. At least one of the 4 slave addresses has been matched by hardware. Software can further check the address if needed, for instance if a subset of addresses qualified by SLVQUAL0 is to be used. Software can ACK or NACK the address by writing 1 to either SLVCONTINUE or SLVNACK. Also see I2C Ten-bit addressing regarding 10-bit addressing.
1 Received data is available (Slave Receiver mode). Read data reply with an ACK or a NACK.
2 Data can be transmitted (Slave Transmitter mode). Send data.
3 Reserved. -

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