I2C MSTTIME addressOffset = 0x024

The MSTTIME register allows programming of certain times that may be controlled by the Master function. These include the clock (SCL) high and low times, repeated Start setup time, and transmitted data setup time.

The I2C clock pre-divider is described in I2C registerName = CLKDIV addressOffset = 0x014.

Table 1. I2C registerName = MSTTIME addressOffset = 0x024
Bit Symbol Value Description Reset value
2:0 MSTSCLLOW   Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t_ LOW in the I^ 2C bus specification. I^ 2C bus specification parameters t_ BUF and t_ SU;STA have the same values and are also controlled by MSTSCLLOW. 0
    0x0 2 clocks. Minimum SCL low time is 2 clocks of the I^ 2C clock pre-divider.  
    0x1 3 clocks. Minimum SCL low time is 3 clocks of the I^ 2C clock pre-divider.  
    0x2 4 clocks. Minimum SCL low time is 4 clocks of the I^ 2C clock pre-divider.  
    0x3 5 clocks. Minimum SCL low time is 5 clocks of the I^ 2C clock pre-divider.  
    0x4 6 clocks. Minimum SCL low time is 6 clocks of the I^ 2C clock pre-divider.  
    0x5 7 clocks. Minimum SCL low time is 7 clocks of the I^ 2C clock pre-divider.  
    0x6 8 clocks. Minimum SCL low time is 8 clocks of the I^ 2C clock pre-divider.  
    0x7 9 clocks. Minimum SCL low time is 9 clocks of the I^ 2C clock pre-divider.  
3 -   Reserved. 0
6:4 MSTSCLHIGH   Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter t_ HIGH in the I^ 2C bus specification. I^ 2C bus specification parameters t_ SU;STO and t_ HD;STA have the same values and are also controlled by MSTSCLHIGH. 0
    0x0 2 clocks. Minimum SCL high time is 2 clock of the I^ 2C clock pre-divider.  
    0x1 3 clocks. Minimum SCL high time is 3 clocks of the I ^ 2C clock pre-divider .  
    0x2 4 clocks. Minimum SCL high time is 4 clock of the I^ 2C clock pre-divider.  
    0x3 5 clocks. Minimum SCL high time is 5 clock of the I^ 2C clock pre-divider.  
    0x4 6 clocks. Minimum SCL high time is 6 clock of the I^ 2C clock pre-divider.  
    0x5 7 clocks. Minimum SCL high time is 7 clock of the I^ 2C clock pre-divider.  
    0x6 8 clocks. Minimum SCL high time is 8 clock of the I^ 2C clock pre-divider.  
    0x7 9 clocks. Minimum SCL high time is 9 clocks of the I ^ 2C clock pre-divider.  
31:7 -   Reserved. Read value is undefined, only zero should be written. NA


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