I2C INTENSET addressOffset = 0x008

The INTENSET register controls which I^ 2C status flags generate interrupts. Writing a 1 to a bit position in this register enables an interrupt in the corresponding position in the STAT register, if an interrupt is supported there. Reading INTENSET indicates which interrupts are currently enabled.

Table 1. I2C registerName = INTENSET addressOffset = 0x008
Bit Symbol Value Description Reset value
0 MSTPENDINGEN   Master Pending interrupt Enable. 0
    0 The MstPending interrupt is disabled.  
    1 The MstPending interrupt is enabled.  
3:1 -   Reserved. Read value is undefined, only zero should be written. NA
4 MSTARBLOSSEN   Master Arbitration Loss interrupt Enable. 0
    0 The MstArbLoss interrupt is disabled.  
    1 The MstArbLoss interrupt is enabled.  
5 -   Reserved. Read value is undefined, only zero should be written. NA
6 MSTSTSTPERREN   Master Start/Stop Error interrupt Enable. 0
    0 The MstStStpErr interrupt is disabled.  
    1 The MstStStpErr interrupt is enabled.  
7 -   Reserved. Read value is undefined, only zero should be written. NA
8 SLVPENDINGEN   Slave Pending interrupt Enable. 0
    0 The SlvPending interrupt is disabled.  
    1 The SlvPending interrupt is enabled.  
10:9 -   Reserved. Read value is undefined, only zero should be written. NA
11 SLVNOTSTREN   Slave Not Stretching interrupt Enable. 0
    0 The SlvNotStr interrupt is disabled.  
    1 The SlvNotStr interrupt is enabled.  
14:12 -   Reserved. Read value is undefined, only zero should be written. NA
15 SLVDESELEN   Slave Deselect interrupt Enable. 0
    0 The SlvDeSel interrupt is disabled.  
    1 The SlvDeSel interrupt is enabled.  
16 MONRDYEN   Monitor data Ready interrupt Enable. 0
    0 The MonRdy interrupt is disabled.  
    1 The MonRdy interrupt is enabled.  
17 MONOVEN   Monitor Overrun interrupt Enable. 0
    0 The MonOv interrupt is disabled.  
    1 The MonOv interrupt is enabled.  
18 -   Reserved. Read value is undefined, only zero should be written. NA
19 MONIDLEEN   Monitor Idle interrupt Enable. 0
    0 The MonIdle interrupt is disabled.  
    1 The MonIdle interrupt is enabled.  
23:20 -   Reserved. Read value is undefined, only zero should be written. NA
24 EVENTTIMEOUTEN   Event time-out interrupt Enable. 0
    0 The Event time-out interrupt is disabled.  
    1 The Event time-out interrupt is enabled.  
25 SCLTIMEOUTEN   SCL time-out interrupt Enable. 0
    0 The SCL time-out interrupt is disabled.  
    1 The SCL time-out interrupt is enabled.  
31:26 -   Reserved. Read value is undefined, only zero should be written. NA


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