I2C INTENCLR addressOffset = 0x00C

Writing a 1 to a bit position in INTENCLR clears the corresponding position in the INTENSET register, disabling that interrupt. INTENCLR is a write-only register.

Bits that do not correspond to defined bits in INTENSET are reserved and only zeroes should be written to them.

Table 1. I2C Interrupt Enable Clear register (INTENCLR, address 0x4005 000C) bit description
Bit Symbol Description Reset value
0 MSTPENDINGCLR Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. 0
3:1 - Reserved. Read value is undefined, only zero should be written. NA
4 MSTARBLOSSCLR Master Arbitration Loss interrupt clear. 0
5 - Reserved. Read value is undefined, only zero should be written. NA
6 MSTSTSTPERRCLR Master Start/Stop Error interrupt clear. 0
7 - Reserved. Read value is undefined, only zero should be written. NA
8 SLVPENDINGCLR Slave Pending interrupt clear. 0
10:9 - Reserved. Read value is undefined, only zero should be written. NA
11 SLVNOTSTRCLR Slave Not Stretching interrupt clear. 0
14:12 - Reserved. Read value is undefined, only zero should be written. NA
15 SLVDESELCLR Slave Deselect interrupt clear. 0
16 MONRDYCLR Monitor data Ready interrupt clear. 0
17 MONOVCLR Monitor Overrun interrupt clear. 0
18 - Reserved. Read value is undefined, only zero should be written. NA
19 MONIDLECLR Monitor Idle interrupt clear. 0
23:20 - Reserved. Read value is undefined, only zero should be written. NA
24 EVENTTIMEOUTCLR Event time-out interrupt clear. 0
25 SCLTIMEOUTCLR SCL time-out interrupt clear. 0
31:26 - Reserved. Read value is undefined, only zero should be written. NA

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