I2C Bus rates and timing considerations

Due to the nature of the I^ 2C bus, it is generally not possible to guarantee a specific clock rate on the SCL pin. On the I2C-bus, the clock can be stretched by any slave device, extended by software overhead time, etc. In a multi-master system, the master that provides the shortest SCL high time will cause that time to appear on SCL as long as that master is participating in I2C traffic (i.e. when it is the only master on the bus or during arbitration between masters).

Rate calculations give a base frequency that represents the fastest that the I^ 2C bus could operate if nothing slows it down.

Rate calculations

SCL high time (in I^ 2C function clocks) = (CLKDIV + 1) * (MSTSCLHIGH + 2)

SCL low time (in I^ 2C function clocks) = (CLKDIV + 1) * (MSTSCLLOW + 2)

Nominal SCL rate = I^ 2C function clock rate / (SCL high time + SCL low time)


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