DEBUG Pin description

The SWD functions are assigned to pins through the switch matrix. The SWD functions are fixed-pin functions that are enabled through the switch matrix and can only be assigned to special pins on the package. The SWD functions are enabled by default.

See SWM Enable an analog input or other special function to enable the analog comparator inputs and the reference voltage input.

Table 1. DEBUG SWD pin description
Function Type Pin Description SWM register Reference
SWCLK I/O SWCLK/PIO0_3/TCLK Serial Wire Clock. This pin is the clock for SWD debug logic when in the Serial Wire Debug mode (SWD). This pin is pulled up internally. PINENABLE0 SWM registerName = PINENABLE0 addressOffset = 0x1C0
SWDIO I/O SWDIO/PIO0_2/TMS Serial wire debug data input/output. The SWDIO pin is used by an external debug tool to communicate with and control the LPC81x. This pin is pulled up internally. PINENABLE0 SWM registerName = PINENABLE0 addressOffset = 0x1C0

The boundary scan mode and the pins needed are selected by hardware (see DEBUG Boundary scan). There is no access to the boundary scan pins through the switch matrix.

Table 2. DEBUG JTAG boundary scan pin description
Function Pin name Type Description
TCK SWCLK/PIO0_3/ TCK I JTAG Test Clock. This pin is the clock for JTAG boundary scan when the RESET pin is LOW.
TMS SWDIO/PIO0_2/ TMS I JTAG Test Mode Select. The TMS pin selects the next state in the TAP state machine. This pin includes an internal pull-up and is used for JTAG boundary scan when the RESET pin is LOW.
TDI PIO0_1/ACMP_I2/ CLKIN/TDI I JTAG Test Data In. This is the serial data input for the shift register. This pin includes an internal pull-up and is used for JTAG boundary scan when the RESET pin is LOW.
TDO PIO0_0/ACMP_I1/ TDO O JTAG Test Data Output. This is the serial data output from the shift register. Data is shifted out of the device on the negative edge of the TCK signal. This pin is used for JTAG boundary scan when the RESET pin is LOW.
TRST PIO0_4/ WAKEUP/TRST I JTAG Test Reset. The TRST pin can be used to reset the test logic within the debug logic. This pin includes an internal pull-up and is used for JTAG boundary scan when the RESET pin is LOW.

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