The RESET pin selects between the JTAG boundary
scan (RESET = LOW) and the ARM SWD debug (RESET =
HIGH). The ARM SWD debug port is disabled while the part is in reset.
To perform boundary scan testing, follow these steps:
- Erase any user code residing in flash.
- Power up the part with the RESET pin pulled
- Wait for at least 250 μs.
- Pull the RESET pin LOW externally.
- Perform boundary scan operations.
- Once the boundary scan operations are completed, assert
the TRST pin to enable the SWD debug mode and release the RESET pin
Note: The JTAG interface cannot be used for debug purposes.
Note: POR, BOD reset, or a LOW on the TRST pin puts the test TAP
controller in the Test-Logic Reset state. The first TCK clock while RESET =
HIGH places the test TAP in Run-Test Idle mode.