|Registers / CRC Register description|
This register is a Read-only register containing the most recent checksum. The read request to this register is automatically delayed by a finite number of wait states until the results are valid and the checksum computation is complete.
|31:0||CRC_SUM||The most recent CRC sum can be read through this register with selected bit order and 1’s complement post-processes.||0x0000 FFFF|
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