ACMP General description

The analog comparator can compare voltage levels on external pins and internal voltages.

The comparator has 4 inputs multiplexed separately to its positive and negative inputs. The multiplexers are controlled by the comparator register CTL (see Comparator block diagram and ACMP registerName = CTRL addressOffset = 0x000).

Comparator block diagram

Reference voltages

The voltage ladder can use two reference voltages, from the VDDCMP or the VDD pin. The voltage ladder selects one of 32 steps between the pin voltage and VSS inclusive. The voltage on VDDCMP should not exceed that on VDD .

Settling times

After the voltage ladder is powered on, it requires stabilization time until comparisons using it are accurate. Much shorter settling times apply after the LADSEL value is changed and when either or both voltage sources are changed. Software can deal with these factors by repeatedly reading the comparator output until a number of readings yield the same result.


The interrupt output comes from edge detection circuitry in this module. Rising edges, falling edges, or both edges can set the COMPEDGE bit and thus request an interrupt. COMPEDGE and the interrupt request are cleared when software writes a 1 to EDGECLR.

Comparator outputs

The comparator output (conditioned by COMPSA bit) can be routed to an external pin. When COMPSA is 0 and the comparator interrupt is disabled, the comparator can be used with the bus clock disabled (SYSAHCLKCTRL) to save power if the control registers don’t need to be written.

The status of the comparator output can be observed through the comparator status register bit.

The comparator output can be routed to the SCT via the switch matrix allowing to capture the time of a voltage crossing or to count crossings in either or both directions. See ACMP Connect the comparator output to the SCT.